By Anupam Chattopadhyay, Rainer Leupers, Heinrich Meyr, Gerd Ascheid
Increasing complexity of recent embedded structures calls for procedure designers to ramp up their layout productiveness with out compromising functionality targets. this can be promoted via sleek digital method point (ESL) strategies. Language-driven Exploration and Implementation of in part Re-configurable ASIPs addresses a tremendous section of the ESL region by means of modeling in part re-configurable processors through high-level structure Description Language (ADL). This procedure additionally tricks an forthcoming evolution within the sector of re-configurable procedure layout.
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Additional info for Language-driven Exploration and Implementation of Partially Re-configurable ASIPs
SIMD VLIW and Non-VLIW: Very Long Instruction Word (VLIW) organization can be applied orthogonally to the pipelined data flow. VLIW is a technique to exploit the spatial parallelism present in the application. The parallel functional units of VLIW are known as slots. Each slot receives a specific instruction to decode and execute. To organize the data coherence between the slots, the storage system is distributed across the slots. Again for each slot, a specific portion of storage can be reserved, leading to clustered storage concept.
The SimpleScalar  tool-set is used to build the simulation environment for Chimaera. The Chimaera compiler is equipped with optimizations like branch collapsing and Single-Instruction- Multiple-Datapath (SIMD). The first optimization enables parallel execution of multiple branches of an application in the re-configurable block. The second optimization leverages the re-configurable block computations of sub-byte range. On top of these optimizations, there is support for identification of application kernels suitable for re-configurable block.
The re-configurable block can be also single-stepped all through or for selected portions. The complete processor debugging is accessible to the software debugger via JTAG interface. NAPA also provides a rich simulation environment for tuning the application and the content of the re-configurable logic . The simulator is specifically targeted for NAPA processor. However, it offers early evaluation and benchmarking opportunity for the software developer. The simulator is built by combining a cycle-accurate RISC simulator of the core processor and an event-driven logic simulator for the re-configurable block.
Language-driven Exploration and Implementation of Partially Re-configurable ASIPs by Anupam Chattopadhyay, Rainer Leupers, Heinrich Meyr, Gerd Ascheid