New PDF release: EDA for IC Implementation, Circuit Design, and Process

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Extra resources for EDA for IC Implementation, Circuit Design, and Process Technology

Sample text

This multivalued decision diagram [66] (MDD)-based approach is implemented in a tool called GYOCRO [65]. 1 Technology-Independent Optimization Typical practical implementations of a logic function utilize a multilevel network of logic elements. A standard-cell-based logic netlist, for example, utilizes such a network. A multilevel logic network can be abstracted as a directed acyclic graph (DAG), with edges representing wires and nodes representing memory elements or combinational logic primitives.

Many technology-independent optimizations can be performed on a multilevel Boolean network. We present several such optimizations, with a brief discussion of the salient techniques for each. 1 Division A function g is a divisor for f if f ϭ gh ϩ r, where r is a remainder function and h a quotient function. Note that h and r may not be unique. If r ϭ 0, we refer to the process as factoring. Division can be of two types: Boolean [13,67,68] or algebraic [13,69,70]. In general, Boolean division explores all possible functions that divide f.

In the early days, logic design involved manipulating the truth table representations as Karnaugh maps [2,3]. The Karnaugh map-based minimization of logic is guided by a set of rules on how entries in the maps can be combined. A human designer can only work with Karnaugh maps containing four to six variables. The first step toward automation of logic minimization was the introduction of the Quine–McCluskey [4,5] procedure that could be implemented on a computer. This exact minimization technique presented the notion of prime implicants and minimum cost covers that would become the cornerstone of two-level minimization.

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