By Bart Vermeulen, Kees Goossens (auth.)
This publication describes an technique and aiding infrastructure to facilitate debugging the silicon implementation of a System-on-Chip (SOC), permitting its linked product to be brought into the industry extra speedy. Readers research step by step the main necessities for debugging a contemporary, silicon SOC implementation, 9 elements that complicate this debugging activity, and a brand new debug technique that addresses those standards and complicating components. The authors’ novel communication-centric, scan-based, abstraction-based, run/stop-based (CSAR) debug method is mentioned intimately, exhibiting the way it is helping to satisfy debug necessities and deal with the 9, formerly pointed out components that complicate debugging silicon implementations of SOCs. The authors additionally derive the debug infrastructure requisites to aid debugging of a silicon implementation of an SOC with their CSAR debug procedure. This debug infrastructure involves a wide-spread on-chip debug structure, a configurable automatic design-for-debug movement for use in the course of the layout of an SOC, and customizable off-chip debugger software program. insurance comprises an review of the potency and effectiveness of the CSAR process and its aiding infrastructure, utilizing six business SOCs and an illustrative, instance SOC version. The authors additionally quantify the rate and layout attempt to help their approach.
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Additional info for Debugging Systems-on-Chip: Communication-centric and Abstraction-based Techniques
9 and present conclusions and future work in Chap. 10. 6 Book Contributions In this book we make the following contributions to the state-of-the-art in post-silicon SOC debug: • We capture the commonly-used post-silicon debug practices in one generic postsilicon debug process and derive its four key debug requirements . • We identify nine factors that complicate the debugging of a silicon SOC implementation using the debug process in Fig. 12 [11, 28, 29, 32]. 22 1 Introduction • We propose a communication-centric, scan-based, abstraction-based, run/stopbased (CSAR) debug approach to address the requirements and the complicating factors of this debug process [13, 28, 29, 35].
A second drawback is the silicon area cost associated with its on-chip hardware components. A run/stop-based debug approach involves stopping the execution of the SOC at an interesting point during its execution and extracting the value of all internal signals via a set of I/O pins afterwards. Support for a run/stop-based debug approach is added to an implementation at design time by (1) adding a (configurable) trigger mechanism that determines when the execution of the SOC is stopped, (2) adding a mechanism to stop the execution of the SOC, (3) adding a mechanism to access the state of the SOC, and (4) adding a mechanism to configure this debug functionality.
In this example, the value of the data output signal “q_b” is regenerated to its new value of logic-1 in the remainder of the clock period to a logic-1 value at t = t2 . 1 Communication Between Two Building Blocks Fig. 4 Example circuit to illustrate meta-stability in a flip-flop 39 clk_a buffer 1 clk_b c_i d_a D Q q_a d_b Q q_b c_j FFB FFA building block A D building block B buffer 2 Fig. 5 First example of meta-stability in a flip-flop ∆t1 d_b clk_b q_b c_i c_j t1 Fig. 6 Second example of meta-stability in a flip-flop t2 t ∆t2 d_b clk_b q_b c_i c_j t1 t3 t flip-flop FFB enough time to correctly evaluate this logic level before the next active edge on the clock signal “clk_b”.
Debugging Systems-on-Chip: Communication-centric and Abstraction-based Techniques by Bart Vermeulen, Kees Goossens (auth.)